1. Field of the Invention
The present invention relates to a method for forming a semiconductor device and, in particular, to a method of manufacturing thin film insulated gate field effect transistors. The thin film transistor can be formed on both an insulating substrate like glass and a semiconductor substrate of single crystal silicon and the like.
2. Description of the Prior Art
Recently, an insulated gate type semiconductor device with a thin film active layer(active region) is studied. Especially a thin film insulated gate transistor, what is called thin film transistor is studied enthusiastically. These are defined as amorphous silicon TFT, crystal silicon TFT, on the basis of material.crystal condition of semiconductor utilized.
Crystal semiconductor has bigger field mobility than that of amorphous semiconductor, and is operated at a high speed. Not only NMOS TFT but also PMOS TFT can be obtained from crystal silicon. Because a CMOS circuit can be formed, a TFT utilizing crystal silicon is studied enthusiastically especially now.
According to achievement until now, in forming an insulated gate device like this, the most appropriate characteristic is obtained by the gate insulating film of a silicon thermal oxidation film. However, it is necessary to heat the film approximately at 1000.degree. C. to obtain the thermal oxidation film. At a temperature like this, substrate material utilized is limited. In forming a TFT like this, an insulating film formed by sputtering and various kinds of chemical vapor deposition(CVD) has been utilized.
Because temperature as high as this is not needed for forming such insulating film as this, restrictions to the substrate is removed. On the other hand, it is problematic that such insulating film formed by this gas phase deposition method has high interface state density and many defects such as pin holes. Concerning repair of such defects and improvement of characteristic, no treatment was done after deposition, and as a matter of fact, mainly solved by making the deposition condition most appropriate.
Recently, researchers interests have been directed to improvement of thin film insulated gate field effect transistors (TFT). For example, it has been proposed in Japanese Patent Application No.Hei4-30220 or Japanese Patent Application No.Hei4-38637 of the same applicants to make the gate electrode from Al, Ti, Cr, Ta or Si and coat the external surface of the gate electrode with oxide films thereof. The source and drain regions of the device are formed by ion implantation with the anoded gate electrode as a mask so that they are located set back from the edge of the gate electrode to provide a so-called offset structure therebetween. The source and drain regions of the device are then laser annealed to recrystallize the same.
The transistors having such an offset structure exhibit excellent characteristics as compared with those having gate electrodes of silicon, tantalum or chromium manufactured without the offset structure. The reproducibility, however, is not so high in this case utilizing the offset structure. The reason for such a low reproducibility is application of a high voltage to the gate electrode during anoding to subject the semiconductor region under a high electric field so that trapping energy states are generated in the semiconductor regions. Although no voltage is particularly applied to the semiconductor region, a voltage of 20 to 150 V is created thereacross due to influence of the high voltage applied to the gate electrode.
This problematic situation will be explained with reference to FIG. 1(A) showing a cross sectional view of a prior art transistor. The transistor comprises a glass substrate 101, a semiconductor film 102 formed on the substrate 101, a gate electrode 104 formed on the semiconductor film 102 through a gate insulating film 103 and an aluminum oxide film 105 formed by anoding of the gate electrode 104 made of aluminum to cover the gate electrode 104. The anoding is carried out by applying a high positive voltage to the gate electrode 104 in an electrolyte which is grounded through a suitable electrode. First, the electric field is caused mainly in the electrolyte around the gate electrode when the anoding is just initiated. The voltage across the semiconductor film 102 is not so high in this stage. When the thickness of the oxide film becomes thick, however, the electric field is concentrated to the oxide film and therefore the voltage across the gate insulating film is increased and causes injection of electrons into the gate insulating film 106 just under the gate electrode 104.
The thickness of the oxide film 105 is, for example, 300 to 400 nm when formed in accordance with the method as described in Japanese Patent Application No. Hei4-30220 or Japanese Patent Application No. Hei4-38637. The thickness of the gate insulating film 103 is, for example, 100 nm. The electric field in the gate insulating film 103 then exceeds the electric field across the aluminum oxide film 105 in this case, assuming that the resistivity of silicon oxide and the resistivity of aluminum oxide are equal to each other, even if the semiconductor region 102 under the gate insulating film 103 is intrinsic and has a certain resistivity to generate a voltage drop thereacross. Because of such a high electric field, the anoding can no longer be continued without damage to the gate insulating film 103.
Furthermore, since an underlying insulating film such as a silicon oxide film is formed between the glass substrate 101 and the semiconductor film 102 in order to prevent undesirable influence of the glass substrate on the semiconductor film 102, particular attention must be paid for formation of the underlying silicon oxide film and the semiconductor films. For example, the silicon oxide film must be formed in order not to contain movable ions. More destructive is existence of trapping states. The elimination of movable ions can be performed to some extent by making the process clean. It is, however, impossible to substantially solve the problem associated with trapping states because the problem originates from the general restriction to the process. The density of interfacial states between the silicon oxide film 103 and the underlying semiconductor films 104 is an important factor which dictates the characteristics of the transistors. In the case of the MOS technique on single crystalline semiconductor substrates, the interfacial state density between the single crystalline semiconductor and a gate oxide film formed on the semiconductor by thermal oxidation is of the order of 10.sup.10 cm.sup.-2. On the other hand, since a corresponding semiconductor is deposited in the form of a polycrystalline silicon on an oxide film formed by plasma CVD, atmospheric pressure CVD or low pressure CVD in the case of the thin film transistors, the interfacial state density is as high as 10.sup.12 cm.sup.-2 or higher. This density is too high to put the transistors into practical use. Namely, if the interfacial state density is so high, several carriers are trapped at the interface and determine the conductivity type of the semiconductor regions irrespective of the gate voltage to increase current leakage therethrough. Accordingly, the underlying silicon oxide film must be formed with such a high quality as required in the case of the gate insulating film. In the case that a silicon oxide film is formed by sputtering or ECR plasma CVD, which is employed in low or intermediate temperature processes where thermal oxidation is not available, the interfacial state density is higher than that in the case of thermal oxidation by about one order of magnitude and therefore a similar problem is inevitable.